The present invention relates to the field of digital memory circuits, and in particular to addressing and sensing memory elements in a cross-point diode memory array.
Many consumer devices are now constructed to generate and/or utilize digital data in increasingly large quantities. Portable digital cameras for still and/or moving pictures, for example, generate large amounts of digital data representing images. Each digital image may require up to several megabytes (MB) of data storage, and such storage must be available in the camera. To provide for this type of data storage application, the storage memory should be relatively low in cost for sufficient capacities of around 10 MB to 1 gigabyte (GB). The storage memory should also be low in power consumption (e.g.  less than  less than 1 Watt) and have relatively rugged physical characteristics to cope with the portable battery powered operating environment. For archival storage, data need only be written to the memory once. Preferably the memory should have a short access time (preferably less than 1 ms) and moderate transfer rate (e.g. 20 Mb/s). Preferably, also, the storage memory should be able to be packaged in an industry standard interface module, such as Personal Computer Memory Card International Association (xe2x80x9cPCMCIAxe2x80x9d) or Compact Flash (xe2x80x9cCFxe2x80x9d) card.
One form of storage currently used for application in portable devices such as digital cameras is Flash memory. This meets the desired mechanical robustness, power consumption, transfer, and access rate characteristics mentioned above. However, a major disadvantage is that Flash memory remains relatively expensive ($1.50-$2 per MB). Because of the price it is generally unreasonable to use Flash memory storage as an archive device, thus requiring data to be transferred from it to a secondary archival storage.
Magnetic xe2x80x9chard discxe2x80x9d storage can be used for archival storage, even in portable devices. Miniature hard disc drives are available for the PCMCIA type III form factor, offering capacities of up to 1 GB. However, such disc drives are still relatively expensive ($0.5 per MB), at least partially because of the relatively high fixed cost of the disc controller electronics. Miniature hard drives have other disadvantages when compared to Flash memory, such as lower mechanical robustness, higher power consumption (xcx9c2 to 4W), and relatively long access times (xcx9c10 mS).
Removable optical storage discs can similarly be used, which offer one large advantage compared to hard disc. The removable optical media is very inexpensive, for example of the order of $0.03 per MB for Minidisc media. However in most other respects optical disc storage compares poorly with magnetic hard discs including relatively poor power consumption, mechanical robustness, bulk, and access performance.
Another form of archival storage is described in co-pending U.S. patent application Ser. No. 09/857,356, entitled xe2x80x9cNon-Volatile Memoryxe2x80x9d, the disclosure of which is hereby incorporated herein by reference. The memory system disclosed therein aims to provide high capacity write-once memory at low cost for archival storage. This is realized in part by avoiding silicon substrates, minimizing process complexity and lowering areal density. The memory system includes a memory module formed of a laminated stack of integrated circuit layers constructed on plastic substrates. Each layer contains cross-point diode memory array, and sensing of the data stored in the array is carried out from a separate integrated circuit remotely from the memory module. In order to address, read from and write to all of the memory elements in the arrays of the various memory module layers, a multiplexing scheme is required to avoid having too many interconnections between the memory module and the remote sensing circuitry.
In conventional integrated circuits multiplexing is accomplished by logic gates synthesized from transistors. It is undesirable to include transistors in a diode based cross-point memory array because they will add to the required processing thereby increasing the fabrication cost. Some of the additional processing may be incompatible with other materials used in the cross-point array. If plastic substrates or organic semiconductors are used to form the cross-point memory array, for example, they may be destroyed by temperatures required for transistor fabrication, or they could be damaged by certain solvents used in a wet etching process. Recently, researchers at Lawrence Livermore Laboratories have demonstrated the fabrication of thin-film-transistors on a plastic substrate, however the process required is much more complicated, and hence more expensive, than the equivalent process required to fabricate diodes.
Electrostatic micro-relays have been developed for a number of applications including power relays for automotive application, and small signal switching for instrumentation and automatic test equipment. Electrostatic micro-relay systems are described, for example, in Wong, Jo-Ey, et al., xe2x80x9cAn Electrostatically-actuated MEMS Switch for Power Applicationsxe2x80x9d, (Micro Electro-Mechanical Systems, 2000. MEMS ""00. Thirteenth IEEE. 2000), and Zavracky, P. M., et. al., xe2x80x9cMicro-mechanical switches fabricated using nickel surface micro-machiningxe2x80x9d, (Micro-electromechanical Systems, Journal of, 1997.6(1): p3-9). The principle advantages of this technology are low power consumption and simplicity of construction. The processing for these devices is still more significant than that required for a simple diode array, however, particularly if a low contact resistance is required.
A third possibility, code-word addressing, includes a number of approaches which have been used to minimize the interconnections to a pixelated display. Such systems are described, for example, in the specification of International Patent Application Publication WO 98/44481, and U.S. Pat. No. 5,034,736. In general code word addressing trades off the ratio of addressing lines to array electrodes and the cross-talk between selected and de-selected electrodes. Although these solutions do not offer log-base-2 reduction in interconnect, they may offer better than 10:1 ratio of electrode to address line, while maintaining a 4:1 cross-talk ratio. Although these solutions are relatively simple to implement, they require a higher number of address lines for a given number of addressed lines than the true multiplexing schemes described previously. A further disadvantage is the cross-talk introduced between addressed and non-addressed memory elements, which makes it difficult to read and write a particular memory element.
In accordance with the principles of the present invention, there is provided an addressing circuit for addressing a cross-point memory array having first and second sets of electrodes arranged so that each electrode in the first set crosses over each electrode in the second set and a respective memory element is formed at each crossing point of the electrodes from the first and second sets. The addressing circuit includes a first set of address lines and a plurality of first diode elements coupled between the first set address lines and the first set electrodes. Each of said first set electrodes are coupled by said first diode elements to a respective unique subset of the first set address lines. The addressing circuit also includes a second set of address lines and a plurality of second diode elements coupled between the second set address lines and the second set electrodes, wherein each of said second set electrodes are coupled by said second diode elements to a respective unique subset of the second set address lines.
Preferably, the addressing circuit includes an address application circuit adapted to apply predetermined voltages to selected subsets of the first and second set address lines, and a sensing circuit coupled to the first and second set address lines for sensing an electrical current in the address lines resulting from said applied voltages to thereby determine a binary state of an addressed memory element in the memory array based on the sensed electrical current.
The addressing circuit preferably also includes a memory writing circuit coupled to the first and second sets of address lines and the first and second set electrodes, the memory writing circuit being adapted to apply predetermined write voltages to the first and second sets of electrodes and a selection voltage to selected subsets of the first and second set address lines, the predetermined write voltage being sufficient to effect a permanent and substantial change in resistance of an addressed memory element in the array determined by the selected subsets.
In a preferred form of the addressing circuit the first diode elements have anodes coupled to the respective first set memory array electrodes and cathodes coupled to the respective first set address lines, and the second diode elements have cathodes coupled to the respective second set memory array electrodes and anodes coupled to the respective second set address lines.
Preferably the cross-point memory array comprises an array of diode based memory elements formed at cross-points of electrodes from the first and second sets, with ends of the electrodes coupled to power supply connections through respective resistive elements. The power supply connections can then be arranged in power supply striping groups to enable power to be selectively supplied to portions of the cross-point array.
In accordance with the present invention, there is also provided a memory circuit including a cross-point memory array having first and second sets of transverse electrodes with respective memory elements formed at the crossing-points of the first and second set electrodes, each memory element including, in at least one of its binary states, a diode element. The memory circuit includes an addressing circuit having a first set of address lines with first diode connections between the first set address lines and the first set memory array electrodes, wherein the first diode connections couple each memory array electrode in the first set to a respective unique subset of the first set address lines. A second set of address lines are provided with second diode connections between the second set address lines and the second set memory array electrodes, the second diode connections coupling each memory array electrode in the second set to a respective unique subset of the second set address lines. The memory circuit also has a read/write circuit adapted to apply predetermined voltages to selected subsets of the first and second set address lines, and including a sensing circuit coupled to the first and second set address lines for sensing an electrical current in the address lines resulting from the applied voltages to thereby determine a binary state of an addressed memory element in the array based on the sensed electrical current.
The read/write circuit may further include a memory writing circuit coupled to the first and second sets of address lines and the first and second set electrodes, the memory writing circuit being adapted to apply predetermined write voltages to the first and second sets of electrodes and a selection voltage to selected subsets of the first and second set address lines, the predetermined write voltage being sufficient to effect a permanent and substantial change in resistance of an addressed memory element in the array determined by the selected subsets.
An integrated circuit can be constructed including the memory circuit, wherein the memory array and addressing circuit are formed in the same fabrication process. In a preferred form of the invention, the integrated circuit is formed on a dielectric substrate surface.
In accordance with the present invention, there is also provided a method for reading data from, or writing data to, a cross-point memory array having first and second sets of electrodes from first and second sets of address lines. The method includes forming first diode connections between the first set address lines and the first set memory array electrodes, wherein the first diode connections couple each memory array electrode in the first set to a respective unique subset of the first set address lines. Second diode connections are formed between the second set address lines and the second set memory array electrodes, the second diode connections coupling each memory array electrode in the second set to a respective unique subset of the second set address lines. In the case of reading data from the array, predetermined voltages are applied to selected subsets of the first and second set address lines, to enable sensing of an electrical current in the address lines resulting from the applied voltages to thereby determine a binary state of an addressed memory element in said array based on the sensed electrical current. In the case of writing data to the array, predetermined write voltages are applied to the memory array electrodes and selection voltages to selected subsets of the first and second set address lines, the predetermined write voltage being sufficient to effect a permanent and substantial change in resistance of an addressed memory element in said array. The addressed memory element is determined by the particular subsets of the first and second set address lines to which selection voltages are applied.